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19-2119; Rev 0; 8/01
Flash Programmable 12-Bit Integrated Data-Acquisition Systems
General Description
The MAX7651/MAX7652 are complete 12-bit data-acquisition systems featuring an algorithmic, switched-capacitor, analog-to-digital converter (ADC), a pulsewidth-modulated digital-to-analog converter (DAC), three timer/counters, and an industry-standard 8051 microprocessor core with a variety of I/O peripherals. Powerdown capability and full functionality with supply voltages as low as +3V make the MAX7651/MAX7652 suitable for portable and power-sensitive applications. The MAX7651/MAX7652 perform fully differential voltage measurements with 12-bit resolution, programmable gain, and separate track-and-hold for both positive and negative inputs. The converter accepts versatile input modes consisting of four 2-channel signal pairs or eight 1-channel signals relative to a floating common. The MAX7651/MAX7652 microprocessor systems feature a CPU, 256 bytes of RAM, two 8kB flash memory, four 8-bit I/O ports, two UARTs, an interrupt controller, and a watchdog timer. Only four clock cycles are required to complete each microprocessor instruction. The MAX7651/MAX7652 are available in 64-pin TQFP packages.
Features
o 12-Bit 53ksps ADC with Fully Differential Inputs o Dual 8-Bit PWM DAC Outputs o Three Timers o 4-Clock Cycle 8051-Compatible Instruction Set with Dual Data Pointers o o o o Programmable Watchdog Supervisor Four Parallel I/O Ports Dual Serial I/O Ports (up to 375kb) +3V or +5V Single-Supply Operation
MAX7651/MAX7652
o DC to 12MHz Clock Speed o 64-Pin TQFP Package
Ordering Information
PART MAX7651CCB MAX7651ECB MAX7652CCB MAX7652ECB TEMP. RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 64 TQFP 64 TQFP 64 TQFP 64 TQFP
Applications
Hand-Held Instruments Portable Data-Acquisition Systems Temperature Controllers Smart Transmitters Data Loggers Multi-Channel Data-Acquisition with Data Formatting
Pin configuration appears at end of data sheet.
Functional Diagram
UPPER 8k BYTE FLASH 2000H- 3FCOH LOWER 8k BYTE FLASH 0000H- 1FFFH 8051 CPU
MAX7651 MAX7652
FOUR 8-BIT I/O PORTS
256 BYTES RAM
EXT MEM SFR BUS MEMORY ADDRESS AND DATA BUSES INTERRUPT CONTROLLER AIN0 12-BIT A/D CONVERTER ANALOG INPUTS AIN7 REF+ REFACOM INT0 INT1
WATCHDOG TIMER
SERIAL PORT 0
SERIAL PORT 1
TIMER 0 TIMER 1 TIMER 2 T2_OUT
PULSEWIDTH MODULATOR
TXD
RXD TXD
RXD
T0 T1 T2 T2_OUT
PWMA PWMB OUTPUT OUTPUT
________________________________________________________________ Maxim Integrated Products
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
ABSOLUTE MAXIMUM RATINGS
AVDD, PWMV, DVDD to AGND_ ..............................-0.3V to +6V AVDD, DVDD to DGND..............................................-0.3V to +6V AVDD to DVDD .......................................................-0.3V to +0.3V AGND, PWMG to DGND .......................................-0.3V to +0.3V Analog Inputs (AIN_, ACOM, XTAL1, XTAL2) to AGND................................................-0.3V to AVDD_ + 0.3V Analog Outputs (PWMA, PWMB) to AGND_..............................................-0.3V to AVDD_ + 0.3V Digital I/O (A_, AD_, ALE/PROG, EA/VPP, INT0, INT1, P_._, PSEN, RST) to DGND ..........-0.3V to DVDD + 0.3V REF+, REF- to AGND_ ..............................-0.3V to AVDD_ + 0.3V Short-Circuit Duration (PWM_, P_._, ALE/PROG, PSEN)..........1s Continuous Power Dissipation (TA = +70C) 64-Pin TQFP (derate 5.00mW/C above +70C).........500mW Operating Temperature Range MAX765_CCB ....................................................0C to +70C MAX765_ECB .................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX7651 AVDD = VPWMV = DVDD = VREF+ = +4.5V to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652 AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC ACCURACY Resolution RES Differential Relative Accuracy (Note 1) INL Single-ended Differential Nonlinearity (Note2) Offset Error (Note 2) Offset Temperature Coefficient Gain Error (Note 2) Gain Temperature Coefficient Channel-to-Channel Matching (Note 2) Offset and gain 3 0.25 DNL Differential Single-ended MAX7651 MAX7652 MAX7651 MAX7652 0.5 0.5 2.3 0.25 3 12 1.5 1.0 4.0 1.5 1 1 7 LSB LSB LSB/C % ppm/C LSB LSB bits SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (53ksps, 1kHz SINE-WAVE INPUT, 5Vp-p (MAX7651), 2.5Vp-p (MAX7652)) Signal-to-Noise + Distortion Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth SINAD THD SFDR Differential Single-ended All unaliased harmonics Differential Single-ended (Note 3) -3dB rolloff Differential Single-ended 71 67 -78 -73 81 79 -85 1 1 dB dB dB dB MHz MHz
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
ELECTRICAL CHARACTERISTICS (continued)
(MAX7651 AVDD = VPWMV = DVDD = VREF+ = +4.5V to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652 AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CONVERSION RATE Conversion Time Conversion Rate ANALOG INPUTS (AIN0-AIN7, ACOM) Input Voltage Range Common-Mode Range Input Current Input Capacitance DIGITAL INPUTS Input Voltage Low VIL -0.5 0.2 x (DVDD + 0.9) 0.7 x (DVDD + 0.1 90 170 0.2 x (DVDD - 1) DVDD + 0.5 V Input high voltage, XTAL and RST Internal Reset Pulldown Resistance Logical High-to-Low Transition Current Logical Zero Input Current, Ports 1, 2, and 3 ALE, PSEN Input Leakage Current, Port 0 Input Capacitance DIGITAL OUTPUTS Output Low Voltage Output High Voltage VOL VOH ISINK = 4mA MAX7651: ISOURCE = 4mA MAX7652: ISOURCE = 2mA 2.4 2.4 0.45 V V IIN MAX7651 MAX7652 Guaranteed by design DVDD + 0.5 409 490 750 k A V CIN 10 0 0 AVDD AVDD 1 V V A pF tCONV fXTAL = 12MHz fXTAL = 12MHz 18.7 53.6 s ksps SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX7651/MAX7652
Input high voltage, except XTAL and RST Input Voltage High VIH
RRST ITL
(Note 4)
75
A
VIN = DVDD or DGND 10
10
A pF
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
ELECTRICAL CHARACTERISTICS (continued)
(MAX7651: AVDD = VPWMV = DVDD = VREF+ = +4.5V to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Reference Voltage Range Reference Input Current Reference Input Capacitance POWER REQUIREMENTS Analog Supply Current Digital Supply Current Idle-Mode Digital Supply Current Stop-Mode Supply Current Analog Power-Supply Rejection Ratio PWM OUTPUTS Output Low Voltage Output High Voltage Program Pulse Width Program Address and Data Setup tPROGL tASUW Guaranteed by design MAX7651 Program Cycle Time tWRITE MAX7652 Verify Address and Data Set Verify Access Time Minimum P2.7 Pulse Width Low Minimum P2.7 Pulse Width High Clock Period Erase Mode Setup Program Pulse Width Erase Cycle Time tADSUR tREAD tP27L tP27H tCK tP23SU tERASLOW tMASSERASE Guaranteed by design 10tCK 3tCK 83 3tCK 10tCK 8.29 11 250 ISINK = 2mA ISOURCE = 2mA 2.4 10tCK 3tCK 7tCK + 54000 7tCK + 54000 3tCK 9tCK + 50 16tCK + 72000 32tCK + 72000 0.4 V V ns ns PSRR MAX7651, during page erase MAX7652, during page erase MAX7651 MAX7652 IAVDD + IDVDD (Note 5) -40 13 5 5 55 40 30 12 10 mA mA mA A dB 10 SYMBOL CONDITIONS MIN TYP MAX UNITS EXTERNAL VOLTAGE REFERENCE CHARACTERISTICS (REF+, REF-) VREF+ - VREF0 AVDD 35 V A pF
FLASH EXTERNAL PROGRAMMING (FIGURE 1, NOTE 6)
ns
ns ns ns ns ns ns ns ms
FLASH EXTERNAL MASS ERASE (FIGURE 2, NOTE 6)
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
TIMING CHARACTERISTICS
(MAX7651: AVDD = VPWMV = DVDD = VREF+ = +4.5 to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figure 3)
PARAMETER RST Pulse Width (High) EXTERNAL CLOCK Clock Frequency Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time fCK tCLCL tCHCX tCLCX tCLCH tCHCL Guaranteed by design Guaranteed by design 1.5tCLCL 20 0.5tCLCL 15 0.5tCLCL 20 2.5tCLC L - 35 0.5tCLCL - 10 2tCLCL - 15 2tCLCL 35 0 tCLCL 15 3tCLCL 50 10 83 25 25 10 10 12 MHz ns ns ns ns ns SYMBOL CONDITIONS MIN 100 + (64 x tCK) TYP MAX UNITS s
MAX7651/MAX7652
INSTRUCTION TIMING CHARACTERISTICS ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold after PSEN Input Instruction Float after PSEN Address to Valid Instruction In PSEN Low to Address Float tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ ns ns ns ns ns ns ns ns ns ns ns
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
TIMING CHARACTERISTICS (continued)
(MAX7651: AVDD = VPWMV = DVDD = VREF+ = +4.5 to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figure 3)
PARAMETER SYMBOL CONDITIONS tMCS = 0, Guaranteed by design tMCS > 0, Guaranteed by design tMCS = 0 tMCS > 0 tMCS = 0 tMCS > 0 Data Hold After RD tRHDX tMCS = 0 Data Float After RD tRHDZ tMCS > 0 tMCS = 0 ALE Low to Valid Data In tLLDV tMCS > 0 tMCS = 0 Port 0 Address to Valid Data In tAVDV1 tMCS > 0 tMCS = 0 tAVDV2 tMCS > 0 tMCS = 0 ALE Low to RD or WR Low tLLWL tMCS > 0 tMCS = 0 tAVWL1 tMCS > 0 tMCS = 0 tAVWL2 tMCS > 0 0.5tCLCL -5 1.5tCLCL -5 tCLCL - 10 ns 2tCLCL 10 tCLCL - 10 ns 2tCLCL 10 0 tCLCL 10 ns 2tCLCL - 10 2.5tCLCL - 58 ns 1.5tCLCL - 58 + tMCS 3tCLCL - 60 ns 2tCLCL 61 + tMCS 3tCLCL - 60 ns 2tCLCL - 64 + tMCS 0.5tCLCL + 10 ns 1.5tCLCL + 10 MIN 2tCLCL - 20 tMCS - 20 2tCLCL - 20 tMCS - 20 2tCLCL - 55 tMCS - 55 ns TYP MAX UNITS
MOVX TIMING CHARACTERISTICS (Note 6) RD Pulse Width WR Pulse Width tRLRH tWLWH ns ns
RD Low to Valid Data In
tRLDV
ns
Port 2 Address to Valid Data In
Port 0 Address Valid to RD or WR Low
Port 2 Address Valid to RD or WR Low
6
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
TIMING CHARACTERISTICS (continued)
(MAX7651: AVDD = VPWMV = DVDD = VREF+ = +4.5 to +5.5V, VREF- = 0, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = +2.7V to +3.6V, VREF+ = +2.5V, VREF- = 0, ACOM = AVDD/2, fXTAL = 12MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Figure 3)
PARAMETER Data Valid to WR Transition SYMBOL tMCS = 0 tQVWX tMCS > 0 tMCS = 0 Data Valid Before WR High tQVWH tMCS > 0 tMCS = 0 Data Hold After WR High tWHQX tMCS > 0 RD Low to Address Float tRLAZ tMCS = 0 RD or WR High to ALE High tWHLH tMCS > 0 SERIAL PORT TIMING CHARACTERISTICS Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Input Data Hold after Clock Rising Edge Clock Rising Edge to Input Data Valid tXLXL tQVXH tXHQX tXHDX tXHDV SM2 = 0 (12 clocks/cycle) SM2 = 1 (4 clocks/cycle) SM2 = 0 (12 clocks/cycle) SM2 = 1 (4 clocks/cycle) SM2 = 0 (12 clocks/cycle) SM2 = 1 (4 clocks/cycle) SM2 = 0 (12 clocks/cycle) SM2 = 1 (4 clocks/cycle) SM2 = 0 (12 clocks/cycle) SM2 = 1 (4 clocks/cycle) 12 tCLCL 4 tCLCL 10 tCLCL 3 tCLCL 2 tCLCL tCLCL tCLCL tCLCL 11tCLCL 3tCLCL ns ns ns ns ns 0 tCLCL -5 CONDITIONS MIN -9 tCLCL - 12 2tCLCL - 20 ns tMCS - 30 tCLCL - 18 ns 2tCLCL - 18 0 10 ns tCLCL + 11 ns ns TYP MAX UNITS
MAX7651/MAX7652
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the offset and gain errors have been nullified. Note 2: AVDD = +5.0V, (VREF+) - (VREF-) = +5.0V or AVDD = +3.0V, (VREF+) - (VREF-) = +2.5V. Note 3: Ground at "ON" channel; 10kHz sine-wave applied to all "off" channels. Note 4: ALE and PSEN are in reset cycle. Note 5: All digital inputs are at DGND or DVDD. fXTAL = 0. Note 6: Table 1. Data Memory Stretch Values. Note 7: The minimum frequency when writing to the internal flash is 4MHz.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 1. Data Memory Stretch Values
MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 MEMORY CYCLES 2 3 (default) 4 5 6 7 8 9 READ/WRITE STROBE WIDTH (CLOCKS) 2 4 8 12 16 20 24 28 STROBE WIDTH TIME AT 12MHz 167ns 334ns 668ns 997ns 1330ns 1666ns 2000ns 2333ns tMCS 0tCLCL 4tCLCL 8tCLCL 12tCLCL 16tCLCL 20tCLCL 24tCLCL 28tCLCL
Table 2. External Flash Programming Modes
MODE Write Lower FLASH Read Lower FLASH Write Lock Bit 1 Write Lock Bit 2 Write Lock Bit 3 Mass Erase Read Sig Bytes Write Upper FLASH Read Upper FLASH RST H H H H H H H H H PSEN L L L L L L L L L ALE/PROG H H H EA/VPP H H H H H H H H H P2.6 L L H H H H L L L P2.7 H H H L L L H P3.6 H H H L H L L H H P3.7 H H H L L L L H H P2.5 L L H H H H L H H
Note 1: To program the lock bits, ALE must be low for duration of "Write Lockbit" cycle. Note 2: INT0 and INT1 are open-drain and must either be driven or require a pullup (typically 10k) to DVDD.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
PROGRAMMING tERASLOW ALE/ ~PROG tP23SU 3tCK (min) ~EA/VPP (LOGIC "1")
~PSEN
P2.6
P2.7
P3.6
P3.7 P2.5 P3.4 (READY/~BSY) tMASSERASE
Figure 1. FLASH External Mass Erase Waveforms
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
P1.0-P1.7 92.0-P2.4 P2.5 LOWER = L UPPER = H PORT 0
PROGRAMMING ADDRESS
VERIFICATION ADDRESS
DATA IN tPROGL
DATA OUT
ALE/~PROG tADSUW 3tCK (min) EA/Vpp (LOGIC "1") tWRITE P2.7 (READ CYCLE) tP27L 10tCK (min) P3.4 (READY/~BSY) tREAD tP27H 3tCK (min) tADSUR
Figure 2. FLASH External Programming and Verification Waveforms
tLHLL ALE tAVLL
tLLIV
tPLPH tPLIV
PSEN
tLLPL tPLAZ
tPXIZ
tPXIX tLLAX PORT 0 ADDRESS A0-A7 tAVIV INSTRUCTION IN ADDRESS A0-A7
PORT 2
ADDRESS A8-A15 OUT
ADDRESS A8-A15 OUT
Figure 3a. External Program Memory Read Cycle 10 ______________________________________________________________________________________
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
tLLDV ALE tWHLH PSEN tLLWL tRLRH tRLDV RD tRLAZ tRHDX tRHD2 PORT 0 INSTRUCTION IN ADDRESS A0-A7 tAVDV1 tAVDV2 PORT 2 DATA IN ADDRESS A0-A7
ADDRESS A8-A15 OUT
Figure 3b. External Data Memory Read Cycle
ALE tWHLH PSEN tWLWH WR
tQVWH PORT 0 INSTRUCTION IN ADDRESS A0-A7 tQVWX tAVWL1 PORT 2 tAVWL2
tWHQX ADDRESS A0-A7
DATA OUT
ADDRESS A8-A15 OUT
Figure 3c. External Program Memory Write Cycle ______________________________________________________________________________________ 11
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.) MAX7651: AVDD = VPWMV = DVDD = VREF+ = 5.0V, VREF- = 0, VCOM = AVDD/2, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = VREF+ = 3.0V, VREF- = 0, VCOM = AVDD/2, fXTAL = 12MHz.
SINGLE-ENDED INL vs. OUTPUT CODE
MAX7651 toc01
DNL vs. OUTPUT CODE
MAX7651 toc02
NEGATIVE GAIN ERROR vs. SUPPLY VOLTAGE
SINGLE-ENDED
MAX7651/2 toc03
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8
0.3 0.2 0.1 0 DNL (LSB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 DIFFERENTIAL
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -2000 -1500 -1000 -500 0 CODE 500 1000 1500 2000
-1.0 -2000 -1500 -1000 -500
0 CODE
500 1000 1500 2000
0
500 1000 1500 2000 2500 3000 3500 4000 4500 CODE
OFFSET ERROR vs. SUPPLT VOLTAGE
MAX7651/2 toc04
OFFSET ERROR vs.TEMPERATURE
MAX7651 toc05
POSITIVE GAIN ERROR vs. SUPPLY VOLTAGE
MAX7651 toc06
1.0
0 -0.1 OFFSET ERROR (LSB) -0.2 -0.3 -0.4 -0.5 -0.6 DIFFERENTIAL
1.0 DIFFERENTIAL 0.5 GAIN ERROR (LSB)
OFFSET ERROR (LSB)
0.5
0
SINGLE-ENDED
SINGLE-ENDED
0
SINGLE-ENDED
-0.5 DIFFERENTIAL -1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-0.5
-0.7 -40 -15 10 35 60 85 TEMPERATURE (C)
-1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
POSITIVE GAIN ERROR vs. TEMPERATURE
MAX7651 toc07
NEGATIVE GAIN ERROR vs. TEMPERATURE
MAX7651 toc08
PWM OUTPUT HIGH vs. SOURCE CURRENT
MAX7651 toc09
0.4 0.2 GAIN ERROR (LSB) DIFFERENTIAL 0 -0.2 -0.4 SINGLE-ENDED -0.6 -0.8 -40 -15 10 35 60
1.4 1.2 DIFFERENTIAL GAIN ERROR (LSB) 1 0.8 0.6 0.4 0.2 0 SINGLE-ENDED
5.000
PWM OUTPUT HIGH (V)
4.950 AVDD = 5V 4.900
4.850
4.800 .-40 -15 10 35 60 85 0 1 2 3 4 5 TEMPERATURE (C) SOURCE CURRENT (mA)
85
TEMPERATURE (C)
12
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.) MAX7651: AVDD = VPWMV = DVDD = VREF+ = 5.0V, VREF- = 0, VCOM = AVDD/2, fXTAL = 12MHz. MAX7652: AVDD = VPWMV = DVDD = VREF+ = 3.0V, VREF- = 0, VCOM = AVDD/2, fXTAL = 12MHz.
PWM OUTPUT HIGH vs. SOURCE CURRENT
MAX7651 toc10
PWM OUTPUT LOW vs. SINK CURRENT
MAX7651 toc11
ANALOG SUPPLY CURRENT vs. INPUT VOLTAGE
MAX7651 toc12
3.000
250
5 ANALOG SUPPLY CURRENT (mA)
PWM OUTPUT LOW (mV)
PWM OUTPUT HIGH (V)
2.950
200 AVDD = 3V 150 AVDD = 5V 100
4
3
2.900 AVDD = 3V 2.850
2
50
1
2.800 0 1 2 3 4 5 SOURCE CURRENT (mA)
0 0 1 2 3 4 5 SINK CURRENT (mA)
0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX7651 toc13
DIGITAL SUPPLY CURRENT vs.TEMPERATURE
MAX7651 toc14
DIGITAL SUPPLY CURRENT vs. CLOCK FREQUENCY
4.5 DIGITAL SUPPLY CURRENT (mA) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
MAX7651 toc15
2.5 AVDD = 5V ANALOG SUPPLY CURRENT (mA) 2.4
11.75 DIGITAL SUPPLY CURRENT (mA)
5.0
11.50
2.3
11.25
2.2
AVDD = 3V
11.00
2.1
10.75
2.0 -40 -20 0 20 40 60 80 85 TEMPERATURE (C)
10.50 -40 -15 10 35 60 85 TEMPERATURE (C)
0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLOCK FREQUENCY (MHz)
IDLE-MODE SUPPLY CURRENT vs. INPUT VOLTAGE
MAX7651 toc16
POWER-DOWN CURRENT vs. INPUT VOLTAGE
MAX7651 toc17
14 IDLE-MODE SUPPLY CURRENT (mA) 12 10 8 6 4 2 0 3.0 3.5 4.0 4.5 5.0
5
POWER-DOWN CURRENT (A)
4
3
2
1
0 5.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 NAME AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AVDD AGND REF+ REFPWMV PWMG PWMA PWMB INT0 INT1 P3.7/RD P3.6/WR P3.5/T1 P3.4/T0/ READY P3.3 P3.2 FUNCTION Analog Input 0. Negative differential input relative to AIN1 or positive differential input relative to ACOM. (See Table 6) Analog Input 1. Positive differential input relative to AIN0 or positive differential input relative to ACOM. (See Table 6) Analog Input 2. Negative differential input relative to AIN3 or positive differential input relative to ACOM. (See Table 6) Analog Input 3. Positive differential input relative to AIN2 or positive differential input relative to ACOM. (See Table 6) Analog Input 4. Negative differential input relative to AIN5 or positive differential input relative to ACOM. (See Table 6) Analog Input 5. Positive differential input relative to AIN4 or positive differential input relative to ACOM. (See Table 6) Analog Input 6. Negative differential input relative to AIN7 or positive differential input relative to ACOM. (See Table 6) Analog Input 7. Positive differential input relative to AIN6 or positive differential input relative to ACOM. (See Table 6) Positive Analog Supply Voltage. Analog power source for the A/D converter and other analog functions excluding the PWM D/A converter. Bypass with a 0.1F in parallel with a 10F low ESR capacitor to AGND. Analog Ground. Connect PWMG to AGND. High-Side Reference Input. High-side reference voltage for A/D conversions. Must be between AVDD and AGND. Bypass to AGND with a 0.1F in parallel with a 10F low ESR capacitor to AGND. Low-Side Reference Input. Low-side reference voltage for A/D conversions. Must be between AVDD and AGND. If not connected to AGND bypass to AGND with a 0.1F in parallel with a 10F low ESR capacitor to AGND. Positive Analog Supply Voltage 2. Analog power source for the the PWM D/A converter outputs. Bypass with a 0.1F in parallel with a 10F low ESR capacitor to PWMG. Ground for PWM. Connect to AGND. PWM Output A. Output of PWM D/A Converter A. See PWM Digital-to-Analog Conversions. PWM Output B. Output of PWM D/A Converter B. See PWM Digital-to-Analog Conversions. External Interrupt 0 Input (active-low) External Interrupt 1 Input (active-low) P3.7: Bit 7 for General Purpose I/O Port 3 (most significant bit) RD: Read Output. Read strobe for accessing external data memory (active-low) P3.6: Bit 6 for General Purpose I/O Port 3 WR: Write Output. Write strobe for writing to external data memory (active-low) P3.5: Bit 5 for General Purpose I/O Port 3 T1: Timer 1 External Input P3.4: Bit 4 for General Purpose I/O Port 3 22 23 24 T0: Timer 0 External Input READY: Ready State Output (external flash programming mode only) P3.3: Bit 3 for General Purpose I/O Port 3 P3.2: Bit 2 for General Purpose I/O Port 3
14
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Pin Description (continued)
PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 NAME P3.1/ TXD0 P3.0/ RXD0 DGND DVDD P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5 P2.6 P2.7 PSEN ALE/ PROG DGND DVDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P3.1: Bit 1 for General Purpose I/O Port 3 TXD0: Transmit Serial Output for Serial Port P3.0: Bit 0 for General Purpose I/O Port 3 (least significant bit) RXD0: Receive Serial Input for Serial Port Digital Ground. Connect DGND to AGND at the power source. Connect pins 27, 39, and 61 together. Positive Digital Supply Voltage. Bypass with a 0.1F in parallel with a 10F low ESR capacitor to DGND. Connect pins 28, 40, and 62 together. P2.0: Bit 0 for General Purpose I/O Port 2 (least significant bit) A8: Bit 8 for Internal Flash Memory Address P2.1: Bit 1 for General Purpose I/O Port 2 A9: Bit 9 for Internal Flash Memory Address P2.2: Bit 2 for General Purpose I/O Port 2 A10: Bit 10 for Internal Flash Memory Address P2.3: Bit 3 for General Purpose I/O Port 2 A11: Bit 11 for Internal Flash Memory Address P2.4: Bit 4 for General Purpose I/O Port 2 A12: Bit 12 for Internal Flash Memory Address P2.5: Bit 5 for General Purpose I/O Port 2 Upper and Lower Internal Flash Memory Select (see Table 2) P2.6: Bit 6 for General Purpose I/O Port 2 Flash Programming Mode Select (see Table 2) P2.7: Bit 7 for General Purpose I/O Port 2 (most significant bit) Flash Programming Mode Select (see Table 2) Program Store Enable (active-low). Qualifies program read from external devices. To ensure flash data integrity during RST insertions, RLOAD must be greater than or equal to 200k. ALE: Address Latch Enable. To ensure flash data integrity during RST insertions, RLOAD must be greater than or equal to 200k. PROG: Flash Memory Program Pulse Digital Ground. Connect pins 27, 39, and 61 together. Positive Digital Supply Voltage. Bypass with a 0.1F in parallel with a 10F low ESR capacitor to DGND. Connect pins 28, 40 and 62 together. P0.0: Bit 0 for General Purpose I/O Port 0 (least significant bit) AD0: Bit 0 for Internal Flash Memory Data or External Memory I/O Data (least significant bit) P0.1: Bit 1 for General Purpose I/O Port 0 AD1: Bit 1 for Internal Flash Memory Data or External Memory I/O Data P0.2: Bit 2 for General Purpose I/O Port 0 AD2: Bit 2 for Internal Flash Memory Data or External Memory I/O Data P0.3: Bit 3 for General Purpose I/O Port 0 AD3: Bit 3 for Internal Flash Memory Data or External Memory I/O Data P0.4: Bit 4 for General Purpose I/O Port 0 AD4: Bit 4 for Internal Flash Memory Data or External Memory I/O Data FUNCTION
MAX7651/MAX7652
38 39 40 41 42 43 44 45
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Pin Description (continued)
PIN 46 47 48 NAME P0.5/ AD5 P0.6/ AD6 P0.7/ AD7 P1.0/T2/ T2OUT/ AD0 P1.1/ T2EX/ AD1 P1.2/ RXD1/ AD2 P1.3/ TXD1/ AD3 P1.4/ AD4 P1.5/ AD5 P1.6/ AD6 P1.7/ AD7 EA/VPP RST XTAL2 XTAL1 DGND DVDD TEST ACOM P0.5: Bit 5 for General Purpose I/O Port 0 AD5: Bit 5 for Internal Flash Memory Data or external memory I/O P0.6: Bit 6 for General Purpose I/O Port 0 AD6: Bit 6 for Internal Flash Memory Data or external memory I/O P0.7: Bit 7 for General Purpose I/O Port 0 (most significant bit) AD7: Bit 7 for Internal Flash Memory Data or external memory I/O P1.0: Bit 0 for General Purpose I/O Port 1 (least significant bit) 49 T2: Timer 2 External Input T2OUT: Timer 2 External Output AD0: Bit 0 for Internal Flash Memory Address P1.1: Bit 1 for General Purpose I/O Port 1 T2EX: Timer 2 External Capture/Reload Trigger AD1: Bit 1 for Internal Flash Memory Address P1.2: Bit 2 for General Purpose I/O Port 1 RXD1: Receive Serial Input for UART 1 AD2: Bit 2 for Internal Flash memory Address P1.3: Bit 3 for General Purpose I/O Port 1 TXD1: Transmit Serial Input for UART 1 AD3: Bit 3 for Internal Flash Memory Address P1.4: Bit 4 for General Purpose I/O Port 1 AD4: Bit 4 for Internal Flash Memory Address P1.5: Bit 5 for General Purpose I/O Port 1 AD5: Bit 5 for Internal Flash Memory Address P1.6: Bit 6 for General Purpose I/O Port 1 AD6: Bit 6 for Internal Flash Memory Address P1.7: Bit 7 for General Purpose I/O Port 1 AD7: Bit 7 for Internal Flash Memory Address EA: Connect to DGND to use external ROM. Connect EA to DVDD for internal flash memory. VPP: Flash Programming Voltage (external flash programming mode only) Active High Reset. Connected to an internal 130k pulldown resistor. Connect a 2.2F (typ) capacitor from DVDD to RST. Clock Output. Connect a crystal across XTAL1 and XTAL2. The on-chip clock signal is not available at XTAL2. Leave XTAL2 unconnected when XTAL1 is driven with an external clock. Clock Input. Connect a crystal across XTAL1 and XTAL2. Alternatively, drive XTAL1 with a CMOScompatible clock and leave XTAL2 unconnected. Digital Ground. Connect pins 27, 39, and 61 together. Positive Digital Supply Voltage. Bypass with a 0.1F in parallel with a 10F low ESR capacitor to DGND. Connect pins 28, 40 and 62 together. Test Point. Must be connected to DGND. Analog Common Input. Negative differential input relative to AIN_ for single-ended measurements (see Table 6). Connect to AVDD/2 for maximum input range. 50 FUNCTION
51
52
53 54 55 56 57 58 59 60 61 62 63 64
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Detailed Description
MAX7651/MAX7652 Architecture
The MAX7651/MAX7652 are complete 12-bit dataacquisition systems featuring an algorithmic, switchedcapacitor, analog-to-digital converter (ADC), dual pulse-width-modulated digital-to-analog converter (DAC), and an industry-standard 8051 microprocessor core with a variety of I/O and timing peripherals. Using an external oscillator with an operating frequency between 1MHz and 12MHz, the MAX7651/MAX7652 execute the majority of its commands in only four clock periods to yield an average speed improvement of 2.5 times over typical 8051 microprocessors requiring 12 clock periods instructions. See the MAX7651/MAX7652 Programmer's Reference Manual for further details. On-chip peripherals include four 8-bit parallel ports, two serial ports, three general-purpose timers, and a watchdog timer. The MAX7651/MAX7652 also feature 16kB in two banks of 8kB flash memory and 256 bytes of high-speed random access memory. Figure 4 shows the program memory organization. When EA is high, the CPU has access to two internal 8kB blocks of flash memory beginning at addresses 0000H (lower block) and 2000H (upper block). Addresses 0000H-0002H and 0003H-006AH of the lower block are reserved for the CPU reset vector and a set of interrupt vectors, respectively (see Table 3). Addresses 3FC0H-3FFFH of the upper block are also reserved and cannot be accessed by the CPU. Addresses 4000H-FFFFH are for external ROM. When EA is low, the external ROM must be used for all program addresses (0000H-FFFFH). Figure 5 shows the data memory (RAM) organization. The first 256 bytes are partitioned between two internal 128-byte blocks. The lower block (addresses 0000H- 007FH) is used for registers or scratchpad memory and can be accessed either directly or indirectly (see the MAX7651/MAX7652 Programmer's Reference Manual ). The upper block (addresses 0080H-00FFH) reflects a set of special function registers (SFRs) when accessed directly, and separate scratchpad memory when accessed indirectly. Addresses 0100H-FFFFH are reserved for external RAM. Table 4 shows the SFR mapping to memory and Table 5 shows the SFR contents on power-up or reset. Unshaded register designations are consistent with the industry standard 8051. Shaded register designations
MAX7651/MAX7652
Memory Organization
The MAX7651/MAX7652 support up to 64kB of external program (read-only) memory and data (randomaccess) memory in conformance with the 8051 industry standard.
FFFFH
EXTERNAL
7FH
LOWER 128 BYTES FFH UPPER 128 BYTES INDIRECT ADDRESSING LOWER 128 BYTES DIRECT AND INDIRECT ADDRESSING SFR SPACE DIRECT ADDRESSING 80H
4000H
DIRECT RAM
FFH
3FFFH 3FCOH
RESERVED UPPER INTERNAL EA = 1
3FFFH EXTERNAL EA = 0 0000H
BANK SELECT 2FH 1FH 17H 0FH 07H 00H BIT-ADDRESSABLE REGISTERS BANK 3 BANK 2 BANK 1 BANK 0 00H
80H 7FH
2000H 1FFFH
LOWER INTERNAL EA = 1
11 10 01
006AH INTERRUPT VECTORS RESET VECTOR 0001H 0002H 0000H
00
0000H
Figure 4. Program Memory Organization
Figure 5. Data Memory (RAM) Organization
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 3. Reset and Interrupt Vector Locations
ADDRESS RANGE 0000H-0002H 0003H-000AH 000BH-0012H 0013H-001AH 001BH-0022H 0023H-002AH 002BH-0032H 0033H-003AH 003BH-0042H 0043H-004AH 004BH-0052H 0053H-005AH 005BH-0062H 0063H-006AH Reset Vector INTERRUPT VECTORS INT0 (external interrupt 0) Timer 0 INT1 (external interrupt 1) Timer 1 Serial Port 0 transmit/receive Timer 2 Reserved Serial Port 1 transmit/receive Flash memory write/page erase ADC (end of conversion) Reserved Reserved Watchdog timer 1 2 3 4 5 6 -- 7 8 9 10 11 12 FUNCTION NATURAL PRIORITY* 0
*Lower priority number takes precedence.
Table 4. SFR Memory Organization
HEX ADDRESS F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 0/8 EIP B EIE ACC EICON PSW T2CON SCON1 IP P3 IE P2 SCON0 P1 TCON P0 SBUF0 EXIF TMOD SP TL0 DPL0 TH0 DPH0 TL1 DPL1 TH1 DPH1 CKCON DPS Reserved PCON SBUF1 RCAP2L ADDAT0 Reserved VERSION RCAP2H ADDAT1 Reserved Reserved Reserved TL2 Reserved TH2 ADCON PWPS PWDA PWDB WDT EEAL EEAH EEDAT EESTCMD 1/9 2/A 3/B 4/C 5/D 6/E PWMC 7/F
Note 1: SFRs in column 0/8 are bit addressable. Other SFRs are not bit addressable. Note 2: The VERSION SFR contains the silicon ID and will change for future MAX7651/MAX7652 revisions.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 5. SFR Contents on Power-Up or Reset
REGISTER ADDRESS P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD TL0 TH0 TL1 TH1 CKCON P1 EXIF SCON0 SBUF0 P2 IE P3 IP SCON1 SBUF1 ADDAT0 ADDAT1 ADCON T2CON RCAP2L RCAP2H TL2 TH2 PSW EICON PWPS PWDTA PWDTB WDT 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 90 91 98 99 A0 A8 B0 B8 C0 C1 C2 C3 C5 C8 CA CB CC CD D0 D8 DA DB DC DD 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 5 1 0 0 0 0 0 0 1 0 0 0 0 0 0 BIT 4 1 0 0 0 0 0 0 1 0 0 0 0 0 0 BIT 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 BIT 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 BIT 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 5. SFR Contents on Power-Up or Reset (continued)
REGISTER ACC EIE EEAL EEAH EEDAT EESTCMD B EIP PWMC ADDRESS E0 E8 EA EB EC ED F0 F8 FE BIT 7 0 1 0 0 0 0 0 1 0 BIT 6 0 1 0 0 0 0 0 1 0 BIT 5 0 1 0 0 0 0 0 1 0 BIT 4 0 0 0 0 0 0 0 0 0 BIT 3 0 0 0 0 0 0 0 0 0 BIT 2 0 0 0 0 0 0 0 0 0 BIT 1 0 0 0 0 0 0 0 0 0 BIT 0 0 0 0 0 0 0 0 0 0
are unique to the MAX7651/MAX7652. Subsequent sections of this data sheet explain the SFR functions. RESERVED SFR addresses are used for MAX7651/ MAX7652 testing and should not be accessed by user software. Undesignated SFR addresses are not implemented and will return indefinite data when read.
No other bits have significance in this register. When SEL= 0, DPTR instructions use DPH0 and DPL0, when SEL=1, DPTR instructions use DPH1 and DPL1. Program code developed for 8051 platforms that use a single data pointer (DPH0 and DPL0) requires no modification if SEL = 0 (the default value). Power Control SFR The PCON Power Control SFR provides software control over the power modes. In both IDLE and STOP modes, CPU processing is suspended and internal registers maintain their current data. The STOP mode additionally disables the internal clock and analog circuitry. Any enabled CPU interrupt can be used to terminate the IDLE mode. A reset is necessary to terminate the STOP mode and is sufficient to terminate the IDLE mode. Table 7 shows the PCON SFR format.
Special Function Registers for Microprocessor Operations and Control
Accumulator SFR The Accumulator SFR is used for arithmetic operations including addition, subtraction, multiplication, division, and Boolean bit manipulation. Accumulator specific instructions designate the accumulator as "A". B SFR The B SFR is used for multiply and divide operations. It is otherwise available as a scratchpad register. Program Status Word SFR The PSW or Program Status Word SFR contains bits that indicate the state of the microprocessor CPU. Table 6 shows the individual bit functions. Stack Pointer SFR The SP or Stack Pointer SFR contains the "top-of-thestack" address in internal RAM. This address increments before data is stored during PUSH and CALL executions. The default value is 07H after reset, so that the stack begins at 08H. Dual Data Pointer SFRs The MAX7651/MAX7652 feature dual data pointers to enhance execution times when moving large blocks of data. All DPTR-related instructions use 16 bits contained at SFR pairs DPH0 and DPL0 or DPH1 and DPL1 to address external data RAM or peripherals. Bit 0 (SEL) within the DPS SFR determines the data pointer.
20
Instruction Set
The MAX7651/MAX7652 instruction set is compatible with the 8051 industry standard. See the MAX7651/ MAX7652 Programmer's Reference Manual for a complete listing.
Analog-to-Digital Converter
ADC Operation Figure 6 shows a simplified model of the converter input structure and the associated switch timing. Once initiated, a voltage conversion requires 224 periods of the external master clock. Capacitor CHOLD charges to the difference between inputs AIN+ and AIN- during eight clock periods of acquisition time that begin on the rising edge of clock cycle 13. This charge sample is subsequently transferred to the ADC (through the action of SW5) during eight clock periods that begin on the rising edge of clock cycle 21. The ADC asserts a conversion complete flag on the rising-edge of clock cycle 225 (see ADC Special Function Registers).
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
VREF+ 1 2 2.1pF CREF 2 VREF1 VREF3 4 AIN5 1.50pF CHOLD VREF+ 3 4 AIN+
CLK
SFR WRITE 1
2
3
4 INPUT SAMPLE 5
Figure 6. ADC Input Structure and Switch Timing
Since the acquisition time is limited to eight clock periods, the acquired voltage at CHOLD can have significant error if the analog input source impedance (Rs) is large. Limit the worst-case error to 1/2 LSB by ensuring, Rs < 0.9 tCLK / CHOLD where tCLK is the clock period. Smaller Rs values may be necessary if an antialiasing filter is used. The ADC continuously samples the positive and negative difference between the two external reference voltages REF+ and REF- by reconfiguring capacitor CREF over alternate eight clock-period intervals. Switch pairs 1 and 2 are forced off and on, respectively, on the rising edge of clock cycle five to ensure synchronization with conversions. Capacitor CHOLD also charges to the difference
between REF+ and REF- on the rising edge of clock cycle 29 and remains charged until the next conversion. Nevertheless, continuous CREF charging requirements dominate loading at the REF+ and REF- inputs. Analog Inputs The MAX7651/MAX7652 operate in either single-ended or differential mode. In single-ended mode, one of eight input channels (AIN0-AIN7) is assigned to AIN+, and ACOM is assigned to AIN- (see Figure 6). In differential mode, the eight input channels are assigned to AIN+ and AIN- with four distinct pairings. Table 6 shows the input assignments for different values of bits M3, M2, M1, and M0 in the A/D Control SFR (see ADC Special Function Registers). Analog Input Protection Internal protection diodes clamp the analog inputs to AVDD and AGND, so channels can swing within AGND 21
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
0.3V and AVDD + 0.3V without damage. For accurate conversions the inputs should not extend beyond the supply rails. Transfer Function Figure 7 shows the bipolar two's complement ADC transfer function. The single-ended conversion range extends from -VREF/2 to +VREF/2, where VREF = VREF+ - VREF-. The differential conversion range extends from -VREF to +VREF. Each LSB in the single-ended and differential mode reflects voltage increments of VREF/4096 and 2VREF/4096, respectively. ADC Special Function Registers The ADCON or A/D Control SFR establishes ADC operating conditions and input configurations. Table 7 shows the individual bit functions. A "write" to ADCON initiates the A/D conversion process.
Table 6. Program Status Word (PSW) Format
BIT 7 (MSB) CY BIT 7 6 5 BIT 6 AC NAME CY AC F0 BIT 5 F0 BIT 4 RS1 BIT 3 RS0 BIT 2 OV BIT 1 F1 BIT 0 (LSB) P
DESCRIPTION Carry Flag. Set to "1", following an additional operation that results in a carry or a subtraction operation that results in a borrow. Otherwise cleared to 0. Auxiliary Carry Flag. Similar to CY, but used for BCD operations. User Flag 0. General-purpose flag for software control. Register Select Bits. These select one of four banks of eight registers that occupy the first 32 addresses in the lower internal RAM. RS1 RS0 0 1 0 1 SELECTED REGISTER BANK Register bank 0, addresses 00H-07H Register bank 1, addresses 08H-0FH Register bank 2, addresses 10H-17H Register bank 3, addresses 18H-1FH
4,3
RS1, RS0
0 0 1 1
2 1 0
OV F1 P
Overflow Flag. Set to "1", for any arithmetic operation that yields an overflow. Otherwise cleared to zero. User Flag 1. General-purpose flag for software control. Parity flag. Set to "1", when the module 2 sum of the accumulator bits is one (odd number of 1's), otherwise clear to zero (even number of 1's).
Table 7. Power Control (PCON) Format
BIT 7 (MSB) SMOD0 BIT 7 6,5,4 3 2 1 0 BIT 6 -- NAME SMOD0 -- GF1 GF0 STOP IDLE Reserved General Flag 1. General-purpose flag for software control. General Flag 0. General-purpose flag for software control. STOP Mode Select. STOP = 1 stops the crystal oscillator and powers down the analog circuitry. IDLE Mode Select. IDLE = 1 results in suspension of CPU processing. BIT 5 -- BIT 4 -- BIT 3 GF1 BIT 2 GF0 BIT 1 STOP BIT 0 (LSB) IDLE
DESCRIPTION Serial Port 0 Baud-Rate Doubler Enable. SMOD0 = 1, doubles the baud rate.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
External Reference
The MAX7651/MAX7652 require external reference voltages at VREF+ and VREF-. A single reference voltage can be used at VREF+, when VREF- is connected to AGND. The positive reference voltages must be no greater than the analog supply voltage AV DD and capable of supplying 30A. Bypass each reference voltage to AGND with a 0.1F capacitor in parallel with a 10F low ESR capacitor.
PWM Digital-to-Analog Converters (DACs)
The MAX7651/MAX7652 provide two pulse-width modulated (PWM) DACs for applications that do not require high conversion accuracy. Figure 8 shows the pulsewidth-modulator block diagram. The clock signal is divided by 2 (x + 1), where x is the content of the Pulse-Width Prescaler (PWPS) SFR register. This reduced frequency signal is used to drive a modulo255 counter. When the counter value exceeds the value stored in SFRs PWDA (Output A) or PWDB
MAX7651/MAX7652
+FS = +VREF 2 -FS = -VREF 2
011 . . . 111 011 . . . 110 1LSB = VREF 4096
011 . . . 111 011 . . . 110
+FS = +VREF -FS = -VREF VREF = (VREF+) - (VREF-)
1LSB = 2VREF 4096
VREF = (VREF+) - (VREF-)
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
VIN = (VAIN) - (VACOM)
VIN = (VAIN+) - (VAIN-)
100 . . . 001 100 . . . 000 -FS 0V INPUT VOLTAGE (LSBs) +FS - 1LSB
100 . . . 001 100 . . . 000 -FS 0V INPUT VOLTAGE (LSBs) +FS - 1LSB
Figure 7a. Single-Ended Mode Transfer Function
Figure 7b. Differential Mode Transfer Function
Table 8. Analog Input Selection
MD3 0 0 0 0 0 0 0 0 1 1 1 1 1 MD2 0 0 0 0 1 1 1 1 0 0 0 0 1 MD1 0 0 1 1 0 0 1 1 0 0 1 1 0 MD0 0 1 0 1 0 1 0 1 0 1 0 1 0 MODE Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential -- AIN+ AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN1 AIN3 AIN5 AIN7 REF+ AINACOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM AIN0 AIN2 AIN4 AIN6 REF-
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
USER ACCESSIBLE SFR REGISTER SFR PWDA REGISTER MAGNITUDE COMPARATOR >= FROM CRYSTAL OSCILLATOR DIVIDE BY TWO MODULO 255 COUNTER MAGNITUDE COMPARATOR >= PWMB OUTPUT PWMA OUTPUT TPWPERIOD = 2(PWPS+1) 255/FOSC TPWHIGH = (255 - PWD(X))/255 x TPWPERIOD FOSC = CRYSTAL FREQUENCY OF X1, X2 PINS TPWHIGH TPWPERIOD
PWPS USER ACCESSIBLE SFR REGISTER
Figure 9. PWM Output Waveform
SFR PWDB REGISTER USER ACCESSIBLE SFR REGISTER
Five watchdog-related control bits and two status flags are located in different special function registers. Table 15 shows the particular functions and SFR locations.
Figure 8. PWM Block Diagram
8051-Compatible Peripherals
Parallel I/O Ports Like other 8051-based systems, the MAX7651/ MAX7652 features four 8-bit parallel ports that support general input and output, address and data lines, and various special functions. Each bidirectional port has a latch register (SFRs P0, P1, P2, and P3), an input buffer, and an output driver. Port P0 is open-drain. Writing a logic level 1 to a P0 pin establishes a high-impedance input. When used as a general-purpose output, a P0 pin requires an external pull-up resistor to validate a logic level 1. When used as an address/data output, a P0 pin features an internal active high driver. Port 0 is a bidirectional Flash data I/O port during Flash programming and verification. Port 1: Port 1 is a bidirectional I/O port with internal pullups. Port 1 pins that have 1's written to them are pulled high by the internal pullups and can serve as inputs. Port 1 receives low-order address bytes during Flash programming and verification. Port 2: Port 2 is a bidirectional I/O port with internal pullups. Port 2 pins that have 1's written to them are pulled high by the internal pullups and can serve as inputs. Port 2 also serves as the high-order address and data bus (for 16-bit operations) during accesses to external memory, using strong internal pullups when emitting 1's. Port 3: Port 3 is a bidirectional I/O port with internal pullups. Port 3 pins that have 1's written to them are pulled high by the internal pullups and can serve as inputs. The P1 and P3 ports support the special functions listed in Table 16. Write a "1" to the corresponding bit in the port register to enable the alternative function.
(Output B), the corresponding output transitions from low to high (Figure 9). Writing 00H to PWDA or PWDB, yields a waveform with 100% duty cycle (High), and writing FFH to PWDA or PWDB yields a waveform with 0% duty cycle (Low). Writing an intermediate register value y, yields a waveform with duty cycle (1 - y / 255) 100%. Tables 10, 11, and 12 show the formats of the PWPS, PWDA, and PWDB SFR's. External low-pass filters are needed to obtain DC voltages between 0 and DV DD from the PWM outputs. Simple RC filters are preferred. Choose R >2k to avoid excessive loading, and choose C <0.1F to avoid large transient currents that reflect the PWM switching action. Each filtered PWM output can source or sink up to 2mA. Do not exceed this specification. If larger output capability is required, provide an appropriate buffer such as a unity-gain op amp. PWM circuitry and PWM Outputs A and B are enabled with the Pulse-Width Modulator Control (PWMC) SFR. Table 13 shows the PWMC SFR format.
Watchdog Timer
The MAX7651/MAX7652 features a watchdog timer that resolves irregular software control. The watchdog timer resets the microprocessor if software fails to reset the timer within one of four pre-selected time intervals. The timer generates an optional interrupt after 216, 219, 222, or 225 clock periods of the external oscillator. It generates the reset signal after an additional 512 clock periods. Table 14 indicates specific interrupt and reset times that apply for a 12MHz clock frequency.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 9. A/D Control (ADCON) Format--SFR Address C5H
BIT 7 (MSB) CC BIT 7 BIT 6 CCVT NAME CC BIT 5 CCIE BIT 4 OVRN BIT 3 M3 BIT 2 M2 BIT 1 M1 BIT 0 (LSB) M0
DESCRIPTION Conversion Complete Flag (Read Only). The MAX7651/MAX7652 set this flag to 1 following a conversion to indicate valid data in the ADDAT1 and ADDAT0 data SFRs (see below). The CC bit is cleared to 0 when ADDAT1 is read by the CPU. Continuous Conversion Enable (Read/Write). When CCVT = 1, the ADC performs continuous conversions at the rate of 224 clock cycles/conversion. Conversions continue until the MAX7651/ MAX7652 is reset or until CCVT is cleared, in which case conversions stops after the current conversion ends. Conversion Complete Interrupt Enable (Read/Write). When CCIE = 1, interrupt 3 is generated at the end of each conversion. Overrun Flag (Read Only). The MAX7651/MAX7652 set this flag to 1 whenever a conversion completes while CC is set. The previous conversion result is overwritten. The OVRN bit is cleared to 0 when ADDAT1 is read by the CPU. Analog Input Multiplexer Select Bits. Used to establish input configurations for single-ended or differential conversions (see Table 6).
6
CCVT
5
CCIE
4
OVRN
3-0
M3-M0
Note: SFRs ADDAT1 and ADDAT0 contain the results of individual A/D conversions with the formats shown in Tables 8 and 9. A read to ADDAT1 clears the CC and OVRN flags in ADCON.
Table 10. A/D Data-1 (ADDAT1) Format--SFR Address C3H
BIT 7 (MSB) SIGN BIT BIT 6 BIT 10 BIT 5 BIT 9 BIT 4 BIT 8 BIT 3 BIT 7 BIT 2 BIT 6 BIT 1 BIT 5 BIT 0 (LSB) BIT 4
Table 11. A/D Data-0 (ADDAT0) Format--SFR Address C2H
BIT 7 (MSB) BIT 3 BIT 6 BIT 2 BIT 5 BIT 1 BIT 4 BIT 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 (LSB) 0
Table 12. Pulse-Width Prescaler (PWPS) Format--SFR address DAH
BIT 7 (MSB) PWPS7 BIT 6 PWPS6 BIT 5 PWPS5 BIT 4 PWPS4 BIT 3 PWPS3 BIT 2 PWPS2 BIT 1 PWPS1 BIT 0 (LSB) PWPS0
Table 13. Pulse-Width Data A (PWDA) Format--SFR address DBH
BIT 7 (MSB) PWDA7 BIT 6 PWDA6 BIT 5 PWDA5 BIT 4 PWDA4 BIT 3 PWDA3 BIT 2 PWDA2 BIT 1 PWDA1 BIT 0 (LSB) PWDA0
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 14. Pulse-Width Data B (PWDB) Format--SFR address DCH
BIT 7 (MSB) PWDB7 BIT 6 PWDB6 BIT 5 PWDB5 BIT 4 PWDB4 BIT 3 PWDB3 BIT 2 PWDB2 BIT 1 PWDB1 BIT 0 (LSB) PWDB0
Table 15. Pulse-Width-Modulator Control (PWMC) Format--SFR Address FEH
BIT 7 (MSB) PWON BIT 7 6-2 1 0 BIT 6 -- NAME PWON -- PWENA PWENB BIT 5 -- BIT 4 -- BIT 3 -- BIT 2 -- BIT 1 PWENA BIT 0 (LSB) PWENB
DESCRIPTION Pulse-Width-Modulator Enable. Set PWON to 1 to enable the divide-by-two, PWPS prescaler, and modulo-255 counter circuit functions. Not used PWM Output A Enable. Set to 1 to enable PWM output A. PWM Output B Enable. Set to 1 to enable PWM output B.
Table 16. Watchdog Interrupt and Reset Times (fCK = 12MHz)
WD1 0 0 1 1 WD0 0 1 0 1 INTERRUPT TIMOUT 216 clocks 219 clocks 222 clocks 225 clocks TIME (ms) 5.461 43.691 349.525 2796.000 RESET TIMOUT 216 + 512 clocks 219 + 512 clocks 222 + 512 clocks 225 + 512 clocks TIME (ms) 5.474 43.734 349.567 2796.042
Serial Interface Ports The MAX7651/MAX7652 each have two serial interfaces that operate according to the 8051 industry standard. Serial Port 0 uses SFRs SCON0 and SBUF0 for control and buffer functions. Serial Port 1 uses SFRs SCON1 and SBUF1 with identical bit functionality. See the MAX7651/MAX7652 Programmer's Reference Manual for details concerning serial-port data operations and timing information. Timers/Counters The MAX7651/MAX7652 have three timer/counters that function in several different modes for applications such as UART baud-rate control. All three timer/counters operate according to the 8051 industry standard. Specifically, the control (TCON), mode (TMOD), timer-0 parameter (TL0, TH0), Timer1 parameter (TL1, TH1), and Timer-2 parameter (TL2, TH2, RCAP2L, RCAP2H) SFRs have conventional formats. See the MAX7651/ MAX7652 Programmer's Reference Manual for information concerning timer/counter applications.
26
Crystal Oscillator
The MAX7651/MAX7652 each have a single-stage inverter (Input at XTAL1, Output at XTAL2) that supports a crystal controlled oscillator. The crystal oscillator frequency should be between 1 and 12 MHz. Note: External flash memory programming requires a minimum crystal oscillator frequency of 4MHz.
Crystal Specification:
Rs(typ) Rs(max) Load Capacitance Oscillation Mode Frequency Tolerance Holder Capacitance Motional Inductance (typ) Motional capacitance (typ) 25-40 150 10-15pF Fundamental 12,000MHz (max) 0.01% 3pF 50mH 0.0035pF
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
An external oscillator can also be used to clock the MAX7651/MAX7652 at frequencies between 1 and 12MHz, provided that the duty cycle is between 40% and 60%. When using an external clock source connect the clock to XTAL1, with XTAL2 unconnected.
Using FLASH Memory
The upper and lower 8kB blocks of internal Flash memory are each organized as 128 64-byte pages. Read, write, and page-erase operations cannot be applied to either block while executing program commands from the other block. Note: Standard MOVC operations are supported. FLASH Memory Special Function Registers Tables 17 and 18 show the formats for the EEAH and EEAL SFRs. The EEAH register specifies the applicable Flash memory block (high or low) and the page address within that block. The EEAL register specifies the byte address within the specified page. Table 19 shows the format for the Flash memory data (EEDAT) SFR that is used for 8-bit read and write transfers from and to a specified address. Table 20 shows the format for the Flash memory status and command (EESTCMD) SFR. Bits RDYHI and RDYLO are cleared to zero when a read, write, or pageerase operation is applied to the high or low flash memory block. These bits are set to one once the flash
MAX7651/MAX7652
Applications Information
Performing a Conversion
An example of a conversion with the MAX7651/ MAX7652 is as follows: * Write to the ADCON SFR, setting bit CCIE to 1, and bits M3-M0 to appropriate values for the desired differential or single-ended analog input configuration (Tables 6 and 7). * Wait 224 clock cycles to receive Interrupt 3 as an indication that the A/D conversion is complete. * Read the conversion data in SFRs ADDAT0 and ADDAT1 as described in Tables 8 and 9.
Table 17. Watchdog Timer Control and Status Bits
NAME SFR BIT DESCRIPTION Watchdog Interrupt Flag. WDIF is set to 1 after completion of the interrupt timeout period (see Table 14). WDIF must be cleared by software before exiting interrupt service routine. Otherwise interrupt reoccurs upon exiting. WDIF is automatically cleared by either an external RST assertion or a WDT-generated reset. Watchdog Reset Flag. The WTRF bit is a status/control bit indicating that the Watchdog counter has counted an additional 512 clocks past the WDT interrupt and has generated a processor RESET. The 8051's "reset" routine should check the WTRF flag to determine the source of the reset. Additionally, if the WTRF flag has been set the Watchdog Timer counts will be reset when a zero is written to the WTRF flag. This allows the processor to regain synchronization with the WDT after a WDT reset has occurred. WTRF is also cleared when a zero is written to it. Enable Watchdog Timer. Set to 1 to enable the watchdog timer. An assertion at the external RST pin automatically clears EWT. If EWT is cleared after being set. The watchdog timer count will suspend until EWT is set to 1 again. Reset Watchdog Timer. Writing a "1" to the RWT bit will reset the watchdog counter ONLY if the end of the count has been reached (WDIF = 1) and the 512 clock window has not expired (WTRF = 0). Writing to RWT before the timeout period will not reset the watchdog timer. Watchdog Control Bit 1. Controls the watchdog interrupt timeout (see Table 14). Watchdog Control Bit 0. Controls the watchdog interrupt timeout (see Table 14). Enable Watchdog Interrupt. An interrupt will be generated after the interrupt timeout period when EWDI = 1. Either a WDT-generated reset or an assertion at the external RST pin automatically clears EWDI.
WDIF
EICON
3
WTRF
WDT
2
EWT
EICON
1
RWT WD1 WD0 EWDI
EICON CKCON CKCON EIE
0 7 6 4
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 18. Alternate Port Functions
PORT PIN P1.3 P1.2 P1.1 P1.0 P3.7 P3.6 P3.5 P3.4 P3.1 P3.0 ALTERNATIVE FUNCTION TXD1 RXD1 T2EX T2/T2_OUT RD WR T1 T0/READY TXD0 RXD0 Transmit Serial Output for Serial Port Receive Serial Input for Serial Sort Timer 2 External Capture/Reload Trigger Timer 2 External Input/Output Read Output Write Output Timer 1 External Input Timer 0 External Input/Ready State Output (External Flash Programming mode only) Transmit Serial Output for UART 0 Receive Serial Input for UART 0 DESCRIPTION
Table 19. Flash Address High (EEAH) Format--SFR Address EBH
BIT 7 (MSB) BLOCK BIT 7 6-0 BIT 6 EEAH6 NAME BLOCK EEAH_ BIT 5 EEAH5 BIT 4 EEAH4 BIT 3 EEAH3 BIT 2 EEAH2 BIT 1 EEAH1 BIT 0 (LSB) EEAH0
DESCRIPTION Flash Memory Block. Set BLOCK = 1 to access the high Flash memory block. Set BLOCK = 0 to access the low Flash memory block. Page Address. Determines the Flash memory page. EEAH6 is the MSB.
Table 20. Flash Address Low (EEAL) Format--SFR Address EAH
BIT 7 (MSB) -- BIT 7,6 5-0 BIT 6 -- NAME -- EEAL_ Not used. Byte within Page Address Bit. Determines the byte address within a Flash memory page. EEAL5 is the MSB. BIT 5 EEAL5 BIT 4 EEAL4 BIT 3 EEAL3 BIT 2 EEAL2 BIT 1 EEAL1 BIT 0 (LSB) EEAL0
DESCRIPTION
memory operation is complete. Never attempt to execute a flash memory command when either RDYHI or RDYLO are 0 (command action in progress). Flash Memory Read To read Flash memory, load the address into SFRs EEAH and EEAL. Then write AAH to EESTCMD. The results of the read operation will be available in SFR EEDAT in the next CPU instruction cycle.
28
Flash Memory Write Erase operations set all bits to "1". After a byte has been programmed it must be erased before it is re-written. To write to Flash memory, load the address into SFRs EEAH and EEAL, and load the data into EEDAT. Then write 55H to EESTCMD. The execution time for flash memory write is 63s (typ) and is independent of the CPU clock.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Note: Do not write to the same location more than twice before the next page/mass erase operation. Flash Memory Page Erase The page erase operation sets all bits within the page to "1"s. To erase a page from Flash memory, load the page address into SFR EEAH, register EEAL is not used. Then write 5AH to EESTCMD. The execution time for page erase is 9.4ms (typ) and is independent of the CPU clock. Note: Do not attempt to apply read, write, or pageerase operations to the flash memory block in which the CPU is currently executing program instructions. 8) Force ALE / PROG low. P3.4 (READY) will go low to indicate a write in progress. 9) When P3.4 returns high (write complete after approximately 63s), set ALE / PROG high. 10) Power-down sequence. A) Remove drive from and allow PSEN and ALE/PROG to float high. B) Pull EA low. C) High-Z all digital pins. D) Remove power from all power pins. Note: Do not write to the same location more than twice before the next page/mass erase operation. External Flash Memory Verify (Table 2) External Verify: If lock bits LB1 and LB2 have not been programmed, the programmed flash array(s) can be read back through the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. External verify (readback) power-up sequence: 1) Power-up the MAX7651/MAX7652 with RST asserted, allow ALE and PSEN to float to the "1" state (they will be internally pulled-up during RST assertion). Wait 10ms for the internal bandgap and oscillator to stabilize. 2) Pull PSEN LOW, EA HIGH, ALE HIGH, and set P2.6, P2.7, P3.6, P3.7, P2.5, as per Flash Programming Modes (Table 2) for reading either LOWER or UPPER flash memory block. Note: P2.7 is cycled low/high to perform a FLASH read operation. Minimum low time for P2.7 is ten clock cycles. External verify power-down sequence: 1) Power-down sequence A)Remove drive from and allow PSEN and ALE/ PROG to float high. B) Pull EA low. C) Hi-z all digital pins. D) Remove power from all power pins.
MAX7651/MAX7652
External Flash Memory Programming
The MAX7651/MAX7652 are normally shipped with the internal Flash memory blocks fully erased (all bits set to 1) and ready for external programming. External write, read (verify), and mass-erase operations are available. Flash memory addresses for either the upper or lower 8-kbyte blocks are specified at Ports 1 and 2. Before applying any external Flash memory operations, power-up the MAX7651/MAX7652 with RST asserted. ALE, PSEN, and ports P1 -P3 are pulled high with weak resistive pullups. Port P0 requires 10k external pullups. Wait at least 10ms for the oscillator and internal circuitry to stabilize. The program, verify and masserase flash memory programming steps are outlined below. Note: Failure to follow proper power-up conditions or the specified flash memory programming steps can result in loss of flash data integrity. External Flash Memory Program (Table 2) Erase operations. Set all bits to "1". After a byte has been programmed it must be erased before it is re-written. 1) Power-up the device with RST asserted and allow ALE and PSEN to float to the "1" state (they will be internally pulled-up during RST assertion). 2) Wait 10ms for the internal bandgap and oscillator to stabilize. 3) Apply the memory location on the address lines at ports 1 and 2. 4) Apply data to the data lines at port 0. 5) Raise EA / VPP to DVDD and pull PSEN low. 6) Set P2.6, P2.7, P3.6, and P3.7 to the levels shown in Table 2. 7) Set P2.5 low or high for the lower or higher 8kB Flash memory block.
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
External Flash Memory Mass Erase A mass erase operation sets all bits, including the lock bits to "1" (Table 22). External Erase: Both FLASH arrays can be simultaneously mass-erased electrically by using the proper combination of control signals as shown in Table 2. The erase operation must be executed before either memory can be programmed. Lock bits are also erased (Set to 1). External chip erase power-up sequence: 1) Power-up chip with RST asserted, and allow ALE and PSEN to float to the "1" state (they will be internally pulled-up during RST assertion). Wait 10ms for the internal bandgap and oscillator to stabilize. 2) Pull PSEN LOW, EA HIGH, set P2.6, P2.7, P3.6, P3.7, and P2.5, as per Mass Erase mode in the Flash Programming Modes (table 2). 3) P3.4 will be LOW during mass erase cycle and return HI at the end of mass erase cycle. External chip erase power-down sequence: 1) Power-down sequence A)Remove drive from and allow PSEN and ALE/ PROG to float high. B) Pull EA low. C) Hi - z all digital pins. D) Remove power from all power pins. Figure 2 shows the timing waveforms that apply for the Flash memory mass erase operation. Flash Memory Lock Bits The MAX7651/MAX7652 each contains three lock bits which can be left unprogrammed (logic "1") or can be programmed (logic "0") to obtain the additional features listed in the table below: When lock bit "1" is programmed (set to logic "0"), the logic level at the EA pin is sampled and latched during RST deassertion. Subsequent changes in logic levels on EA have no effect. If the device is powered-up without a reset (RST), the latch initializes to a random value and holds that value until RST is pulsed high, then low. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Signature Bytes The MAX7651/MAX7652 contain three signature bytes with the information shown in Table 23. Read each byte by following the Flash Memory Read procedure, but set P2.6, P2.7, P3.6, and P3.7 at low. Signature bytes are not affected by mass erase or page erase operations.
Table 21. Flash Memory Data (EEDAT) Format--SFR Address ECH
BIT 7 (MSB) EEDAT7 BIT 6 EEDAT6 BIT 5 EEDAT5 BIT 4 EEDAT4 BIT 3 EEDAT3 BIT 2 EEDAT2 BIT 1 EEDAT1 BIT 0 (LSB) EEDAT0
Table 22. Flash Status and Control (EESTCMD) Format--SFR Address EDH
BIT 7 (MSB) RDYHI/ EECMD7 BIT 7 BIT 6 RDYLO/ EECMD6 NAME RDYHI BIT 5 EECMD5 BIT 4 EECMD4 BIT 3 EECMD3 BIT 2 EECMD2 BIT 1 EECMD1 BIT 0 (LSB) EECMD0
DESCRIPTION High Block Ready Status. The MAX7651/MAX7652 set RDYHI to 0 during read, write, and pageerase operations that are applied to the 8-kbyte "high" block of flash memory. The bit is otherwise set to 1. Low Block Ready Status. The MAX7651/MAX7652 set RDYLO to 0 during read, write, and pageerase operations that are applied to the 8-kbyte "low" block of flash memory. The bit is otherwise set to 1. Flash Memory Command Bits. Used to specify read, write, or page-erase memory commands. EECMD7 is the MSB.
6 7-0
RDYLO EECMD
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Interrupt System
The MAX7651/MAX7652 has ten program-assist interrupts that are either external or internal to the 8051 system. Table 24 shows the SFR bit locations for interrupt enable and priority control. Shaded Table regions reflect the 8051 industry standard. Set SFR bit IE.7 high to enable all interrupts. See the MAX7651/MAX7652 Programmer's Reference Manual. clock cycles needed (four or twelve) to increment each timer/counter or the number of clock cycles needed to execute the MOVX instruction. See the MAX7651/ MAX7652 Programmer's Reference Manual for further details.
MAX7651/MAX7652
Analog and Digital Supplies
The MAX7651/MAX7652 have multiple power-supply inputs: one analog AVDD and three digital DVDD. The pulse width modulators have their own power supply inputs, PWMV and PWMG. Decouple all supply inputs with a 0.1F capacitor in parallel with a 10F low ESR capacitor, with both capacitors as close to the supply pins as possible and with the shortest possible connection to the ground plane.
Timers
The MAX7651/MAX7652 feature several modes of timing control through the CKCON special function register. Table 25 shows the CKCON SFR format. The individual control bits can be used to set the number of
Table 23
PARAMETER TPROGL TASUW TWRITE TADSUR TREAD TP27L TP27H TCK 10TCK 3TCK 83ns 250ns MIN 10TCK 3TCK 7TCK + 54s 3TCK 8TCK + 50ns Read access time 7TCK + 72s MAX COMMENTS TPROGL must equal TWRITE during lockbit writes
Note: P2.6, P2.7, P3.6, and P3.7 must also meet TASUW (min) timing specification.
Table 24. Lock Bit Protection Modes
PROGRAM LOCK BITS LB1 LB2 LB3 1 1 1 1 2 3 4 0 0 0 1 0 0 1 1 0 PROTECTION TYPE No program lock features (Default after a mass erase) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset (RST), and further external data programming of both FLASH arrays is disabled. Verify (read) is disabled. (see Mode 2) External execution is disabled (EA override, see Mode 3).
Table 25. MAX7651/MAX7652 Signature Bits
ADDRESS 30H 31H 32H DATA 7FH CBH 20H MEANING JEDEC Continuation Byte Manufactured by Maxim MAX7651/MAX7652
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Table 26. MAX7651/MAX7652 Interrupts (Note 1)
INTERRUPT INT0 INT1 FLASH ADC WDTI TF0 or EXF0 TF1 or EXF2 TI_0 or RI_0 TF2 or EXF2 TI_1 or RI_1 ASSOCIATED FEATURE External Interrupt 0 External Interrupt 1 Flash Operation Complete A / D Operation Complete Watchdog Timer Timer 0 Timer 1 Serial Port 0 Timer 2 Serial Port 1 ENABLE SFR BIT (NOTE 2) IE.0 IE.2 EIE.0 EIE.1 EICON.1 IE.1 IE.3 IE.4 IE.5 IE.6 PRIORITY SFR BIT (NOTE 3) IP.0 IP.1 EIP.0 EIP.1 EIP.4 IP.1 IP.3 IP.4 IP.5 IP.6 PRIORITY 1 3 8 9 10 2 4 5 6 7
Note 1: Shaded areas reflect the 8051 industry standard. Note 2: Set Enable SFR bit high to enable interrupt. Note 3: Set Priority SFR bit high to eatablish high priority.
Table 27. CKCON SFR Address 8EH
BIT 7 (MSB) WD1 BIT 7 6 5 4 3 2 1 0 BIT 6 WD0 NAME WD1 WD10 TIMER2 TIMER1 TIMER0 MD2 MD1 MD0 Set MD2, MD1, and MD0 to adjust the Read/Write strobe width (in clocks). The number of clock cycles is two plus the MD2, MD1, MD0 decimal value. MD0 is the LSB. BIT 5 TIMER2 BIT 4 TIMER1 BIT 3 TIMER0 BIT 2 MD2 BIT 1 MD1 BIT 0 (LSB) MD0
DESCRIPTION Set WD1 and WD0 to adjust the interrupt interval for the watchdog timer. (See Watchdog Timer.) Timer 2 Control. Set TIMER2 = 1 for TIMER2-associated counter increments at four clock intervals. Set TIMER2 = 0 for increments at 12 clock intervals. Timer 1 Control. Set TIMER1 = 1 for Timer1-associated counter increments at four clock intervals. Set TIMER1 = 0 for increments at 12 clock intervals. Timer 0 Control. Set TIMER0 = 1 for Timer0-associated counter increments at four clock intervals. Set TIMER0 = 0 for increments at 12 clock intervals.
Power Requirements
MAX7651 operates from +5V while the MAX7652 operates from +3V analog and digital supply voltages. The analog supply current is typically 2mA. The typical digital supply currents (continuous A/D conversions at 12MHz clock frequency) are 5mA and 13mA at +3V and +5V, respectively. Current consumption will vary
depending on RAM read/write and flash read/write page erase duty cycle. Idle Mode In idle mode, CPU processing is suspended and internal data registers maintain their current data. However, unlike typical 8051 systems, the clock is not disabled internally. Set PCON.0 (IDLE) high to enter the Idle
32
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
mode after the instruction is complete. Figure 10 shows the related timing characteristics. Enable any interrupt to clear PCON.0 and exit the Idle mode (See Figure 11 for the related timing). Assert RST alternately. Stop Mode In stop mode, the internal clock and analog circuitry are powered-down. Set PCON.1 (STOP) HIGH to enter the Stop mode after the instruction is complete. Figure 12 shows the related timing characteristics. The only way to exit Stop mode is to assert RST.
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX7651/MAX7652 are measured using the best straight-line fit method.
MAX7651/MAX7652
CLK
IDLE PCON.0
MEM ADDR
n
n+1
ALE
-PSEN
Figure 10. Idle Mode Entry Timing
CLK INTO IDLE ALE ~PSEN MEM ADDR ADDRESS OF LAST EXECUTED INSTRUCTION 003H
Figure 11. Idle Mode Exit Timing
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33
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
CLK CPU CYCLE STOP PCON.1 ALE ~PSEN MEM ADDR n n+1 n+2 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4
Figure 12. Stop Mode Timing
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
Effective Number Of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADCs error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Offset Error
The offset error is the difference between the ideal and the actual offset points. For an ADC, the offset point is the midstep value when the digital output is zero.
Gain Error
The gain or full-scale error is the difference between the ideal and actual gain points on the transfer function, after the offset error has been canceled out. For an ADC the gain point is the midstep value when the digital output is full-scale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: 2 2 2 2 V2 + V3 + V4 + V5 THD = 20 x log V1
Signal-To-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADCs resolution (N Bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise including thermal noise, reference noise, clock jitter. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
(
)
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental maximum signal component to the RMS value of the next largest distortion component.
Chip Information
TRANSISTOR COUNT: 358,000 PROCESS: CMOS
Signal-To-Noise Plus Distortion (SINAD)
Signal-To-Noise Plus Distortion is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals.
34
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Flash Programmable 12-Bit Integrated Data-Acquisition Systems
Pin Configuration
P1.0/T2/T2OUT/AD0
MAX7651/MAX7652
P1.3/TXD1/AD3
P1.2/RXD1/AD2
TOP VIEW
P1.7/AD7 P1.6/AD6 P1.5/AD5 P1.4/AD4 EA/VPP ACOM XTAL1 XTAL2 DGND DVDD TEST RST
64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AVDD
P1.1/T2EX/AD1
1 2 3 4 5 6 7 8 9
48 P0.7/AD7 47 P0.6/AD6 46 P0.5/AD5 45 P0.4/AD4 44 P0.3/AD3 43 P0.2/AD2 42 P0.1/AD1 41 P0.0/AD0
AGND 10 REF+ 11 REF- 12 PWMV 13 PWMG 14 PWMA 15 PWMB 16
MAX7651 MAX7652
40 DVDD 39 DGND 38 ALE/PROG 37 PSEN 36 P2.7 35 P2.6 34 P2.5 33 P2.4/A12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
INT0
INT1
A9/P2.1
A10/P2.2
RD/P3.7
WR/P3.6
RXD0/P3.0
READY/T0/P3.4
TXD0/P3.1
64-TQFP
______________________________________________________________________________________
A11/P2.3
T1/P3.5
A8/P2.0
DGND
DVDD
P3.3
P3.2
35
Flash Programmable 12-Bit Integrated Data-Acquisition Systems MAX7651/MAX7652
Package Information
64L, 10x10x1.4 TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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